In standard logic circuitry, such as static and dynamic CMOS logic, nodes are charged and discharged in a completely irreversible, dissipative manner, using a switch to charge a node to a first potential and to discharge the node to a second potential. It has been proposed to attach such a node to a slew rate limited clock which in theory gradually, adiabatically, and reversibly charges and discharges the node. Logic circuitry using this technique is currently too complicated and uses too many transistors so that, at normal speeds of operation, any power savings for each transistor may be lost by the fact that many more transistors are used to accomplish simple logical operations. In addition, it has not been possible to completely avoid nonadiabatic transitions in some prior designs. The total power consumption of the entire circuit thus may not be much less than that used by nonadiabatic circuitry.